Scalable Verification
Mentor provides a complete set of advanced verification methodologies that:
- Improve productivity, predictability and quality
- Are based on standards (eliminate vendor lock-in and support any flow)
- Incorporate the best technology
- Span the entire SOC verification problem
OVM plus Questa in-depth
OVM for SystemVerilog
The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog.
OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and represents interoperability with multiple languages and simulators. OVM is fully open, and includes a robust class library and source code
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The Questa™ advanced verification environment from Mentor Graphics® combines high performance and high capacity with the most advanced verification capabilities in the industry.
Assertion-based verification (ABV), testbench automation, and coverage-driven verification (CDV) are supported by a self-contained assertion engine, an advanced constraint solver, and extensive functional coverage features. This complete set of advanced verification methodologies are enabled by a flexible architecture that is unrivaled in the area of language support.
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Veloce Emulator is one of the Hot 100 Products
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Featured Scalable Verification Techpubs
Getting Started with the OVM 2.0: AVM Backward Compatibility and Migration
This document provides information for existing users of the Advanced Verification Methodology (AVM) users or people familiar with the AVM to begin using the Open Verification Methodology. There are a few levels of compatibility available that we address
Overview of Sequence Based Stimulus Generation in OVM 2.0
This document provides an overview of sequences and shows all the code necessary to use sequences within the OVM.
Realizing Advanced Functional Verification with Questa
Over the past several years, a great deal of effort has gone into the development and deployment of functional verification tools and technologies. However, logical and functional flaws continue to be the leading cause of design spins by a fantastic margin. Yet despite the best efforts of the EDA industry, the problem is getting worse. Between 2002 and 2004 the percentage of designs with functional errors has actually increased.
Current verification tools and technologies are not only failing but also falling further behind the pace of design innovation. In order to reverse this trend, we need to change the way we think about functional verification in general and how we evaluate verification productivity specifically. We need to open the door to a new methodology that represents real value, not merely the re-packaging of distinct and disparate tools.
An advanced verification methodology is made possible by the purposeful application of an integrated set of intelligent methodologies to functional verification. As embodied in the Questa platform from Mentor Graphics, this advanced verification methodology enables users to manage and implement powerful technologies in a complementary way, providing confidence that the myriad corner cases of today's increasingly complex designs are covered.
Technical Events:
- Open Verification Methodology Introduction Workshop
Dec 5, 2008 - Munich, DE
- Eldo RF: Radio Frequency IC Simulation Workshop
Dec 10, 2008 - San Jose, CA
- A Demonstration of ModelSim Designer
- online
- Analyzing Bus Architectures for ARM-based SOC Designs
- online